Semiconductor processing and packaging techniques continue to evolve to meet industry demands for increased performance and reduced size. Electronic products, such as cell phones, smart phones, tablets, personal digital assistances, laptop computers, as well as other electronic devices, require packaged semiconductor assemblies having a high density of devices while having a relatively small footprint. For example, the space available for memory devices, processors, and other devices continues to decrease in electronic products providing a need to increase the density of semiconductor devices. The stacking of semiconductor devices to form a semiconductor device assembly is one technique used to increase the density. Additionally, the thickness of semiconductor devices is continually being decreased.
During the process of forming a semiconductor device assembly, the assembly may go through various processes having an elevated temperature. For example, the temperature during a reflow process to create solder joints, or interconnections, between semiconductor devices may reach 260 degrees Celsius. A semiconductor devices assembly may be comprised of various components such as, but not limited to, a substrate, semiconductor devices, and mold compound. Each of the components may have different coefficients of thermal expansion (CTE). The use of thinner and thinner components may increase the potential problems created by CTE mismatch of the components within a semiconductor device assembly. As the semiconductor device assembly is subjected to an elevated temperature, the semiconductor device assembly may experience warpage due to the different CTEs of the individual components of the assembly. Warpage may provide a large amount of stress on the components of the assembly. If the warpage is too large, the warpage may create reliability issues with the solder joints within the semiconductor device assembly. For example, a warpage larger than, but not limited to, 50 microns may result in solder joint reliability issues.
CTE mismatch may also create problems in connecting a first semiconductor device to a second semiconductor device. The first semiconductor device may have a first warpage at an expected reflow temperature and the second semiconductor device may have a second warpage that differs from the first warpage at the expected reflow temperature. The differences between the first and second warpage may make it very difficult to connect the first semiconductor device to the second semiconductor device.
Additional drawbacks and disadvantages may exist.
While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the intention is to cover all modifications, equivalents and alternatives falling within the scope of the disclosure as defined by the appended claims.